Many applications exist for metallized through-holes in semiconductor wafers. Referring to FIG. 1, in a prior art method for forming metallized vias, metal pads 122 are formed on the first side of a wafer 120 as part of a circuit pattern and holes 124 are etched through the wafer 120 from the second side so that the holes 124 expose a portion of the underside of the pads 122. A conductive metal layer 123 is then deposited to coat the inside of the hole and the surrounding area with metal using ordinary semiconductor processing techniques, such as sputtering or electroless plating. This structure is then electroplated using the metal pads 122 and deposited layer 123 as a cathode to fill up the remainder of the via hole and form a layer 125.
During the electroplating, the higher electric field at the corners where the vertical walls of the holes intersect the horizontal surface of the wafer 120 results in higher current densities and therefore higher plating rates. There are distinct disadvantages that result from this higher electric field. The electroplated metal is deposited more rapidly in regions of higher electric field. As a result, the top of the hole 124 fills in more rapidly than its bottom. Eventually the opening of the hole will close before the bottom of the hole has filled in creating an unmetallized cavity 127 inside of the via. Further, bumps 129 are formed on the surface of the wafer surrounding the holes due also to the higher electric field in these regions.
In another technique proposed by Subbarao, et al., U.S. Pat. No. 4,348,253, the holes used as vias are not terminated by metal pads. Circuit patterns are formed on the front side of the semiconductor wafer. A precision laser then drills the holes one at a time from the front side of the wafer. Because each hole in the wafer must be individually drilled significant processing time is required. Localized heating from the laser may create surface and structural damages within the semiconductor material.
The wafer is then metallized on the backside and mounted on an electroplating block using an insulating adhesive layer. Subsequent electroplating using the backside metallization as a cathode fills the vias from the backside of the wafer. It is possible for a void to be formed in the via hole adjacent to the adhesive layer.
Examples of other techniques of forming metallized vias can be found in the following U.S. Patents. In U.S. Pat. No. 3,562,009 a laser beam is used to drill a hole through a wafer and a metal structure on the surface of the wafer. The drilling vaporizes the metal which becomes deposited on the inner surfaces of the hole. In U.S. Pat. No. 3,323,198 a similar technique to the U.S. Pat. No. 3,562,009 is used with a high energy electron beam.
In U.S. Pat. Nos. 4,512,829, and 4,211,603 techniques are disclosed for forming plated through-holes in printed circuit boards and multi-layer printed circuit boards. In U.S. Pat. No. 4,153,988 a technique is disclosed for forming plated through holes in packages for integrated circuits. In U.S. Pat. No. 3,484,341 a technique is disclosed for forming aluminum contacts in integrated circuits which partially penetrate a semiconductor wafer.
It is an object of the present invention to provide completely metallized vias for a semiconductor wafer without voids, cavities or surface bumps.
It is a further object of the invention to provide completely metallized vias with a simple process flow.
It is yet another object of the invention to provide completely metallized vias terminated by metal pads which are not through-etched.